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| IC61SP12832 IC61SP12836 Document Title 128K x 32 Pipelined SyncBurst SRAM Revision History Revision No 0A History Initial Draft Draft Date Remark September 17,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 1 IC61SP12832 IC61SP12836 128K x 32, 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * PentiumTM or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * 100-Pin TQFP (JEDEC LQFP) and 119-pin PBGA package * Single +3.3V, +10%, -5% power supply * Power-down snooze mode DESCRIPTION The ICSI IC61SP12832,IC61SP12836 are high-speed, lowpower synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the PentiumTM, 680X0TM, and PowerPCTM microprocessors. It is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SP12832,IC61SP12836 and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frenquency -166 3.5 6 166 -150 3.8 6.7 150 -133 4 7.5 133 -117 4 8.5 117 -5 5 10 100 Units ns ns MHz ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 BLOCK DIAGRAM MODE Q0 A0' CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 128K x 32, 128K x 36 MEMORY ARRAY 15 17 A16-A0 17 D Q ADDRESS REGISTER CE CLK 32 32 GW BWE BW4 DQd BYTE WRITE REGISTERS CLK D Q BW3 D DQc Q BYTE WRITE REGISTERS CLK BW2 DQb BYTE WRITE REGISTERS CLK D Q BW1 D DQa Q BYTE WRITE REGISTERS CLK CE CE2 CE2 D Q 4 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 32 DQ[31:0] D Q ENABLE DELAY REGISTER CLK OE Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 3 IC61SP12832 IC61SP12836 PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin LQFP 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ 2 3 4 5 6 7 A6 CE2 A7 NC DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 NC A5 NC NC A4 A3 A2 GND GND GND BW3 GND NC GND BW4 GND GND GND MODE A10 NC ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A11 NC A8 A9 A12 GND GND GND BW2 GND NC GND BW1 GND GND GND NC A14 NC A16 CE2 A15 NC DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 NC A13 NC NC VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ VCCQ NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 NC 128K x 32 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GNDQ GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable Isolated Output Buffer Ground CE, CE2, CE2 Synchronous Chip Enable A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE 4 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin LQFP 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ 2 3 4 5 6 7 A6 CE2 A7 NC DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 NC A5 NC NC A4 A3 A2 GND GND GND BW3 GND NC GND BW4 GND GND GND MODE A10 NC ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A11 NC A8 A9 A12 GND GND GND BW2 GND NC GND BW1 GND GND GND NC A14 NC A16 CE2 A15 NC DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 NC A13 NC NC VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ VCCQ DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 DQPa 128K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable GW OE DQa-DQd MODE VCC GND VCCQ ZZ GNDQ DQPa-DQPd Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable Isolated Output Buffer Ground Parity Data I/O CE, CE2, CE2 Synchronous Chip Enable A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 5 IC61SP12832 IC61SP12836 TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X 0 H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L H H L H H H H X X H X H H X X H X L X X L L X 0 L H H H H H H H H H H H H ADV WRITE X X X X X X X X L L L L L L H H H H H H X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z Q High-Z High-Z High-Z Q High-Z Q High-Z High-Z High-Z PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 BW4 X H H L X X H H L X 6 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value -40 to +85 -55 to +150 1.6 100 -0.5 to VCCQ + 0.3 -0.5 to VCC + 0.5 -0.5 to 4.6 Unit C C W mA V V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 7 IC61SP12832 IC61SP12836 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V, +10%, -5% 3.3V, +10%, -5% DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VIN VCCQ(2) Com. Ind. Test Conditions IOH = -4.0 mA IOL = 8.0 mA Min. 2.4 -- 2.0 -0.3 -2 -5 -2 -5 Max. -- 0.4 VCCQ + 0.3 0.8 2 5 2 5 Unit V V V V A A GND VOUT VCCQ, OE = VIH Com. Ind. POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Vcc = Max. Cycle Time tKC min. Device Deselected, VCC = Max., All Inputs = VIH or VIL CLK Cycle Time tKC min. ZZ = VCCQ Clock Running All Inputs GND + 0.2V or Vcc - 0.2V Com. Ind. -166 Typ. Max. 200 230 ---- -150 Typ. Max. 190 220 200 230 -133 Typ. Max. 180 210 190 220 -117 Typ. Max 175 205 185 215 -5 Typ. Max. 170 200 180 210 Unit mA mA ISB Standby Current Com. Ind. 45 -- 70 -- 45 50 70 80 45 50 70 80 45 50 65 75 45 50 65 75 mA mA IZZ Power-down Mode Current Com. Ind. -- -- 5 15 -- -- 5 15 -- -- 5 15 -- -- 5 15 -- -- 5 15 mA mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCCQ. 2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V. 8 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 3.3V 317 ZO = 50 OUTPUT Output Buffer 30 pF 50 1.5V 5 pF Including jig and scope 351 Figure 1 Figure 2 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 9 IC61SP12832 IC61SP12836 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 Symbol Parameter fMAX tKC tKH tKL tKQ tKQX (1) Min. -- 6 2.4 2.4 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max. 166 -- -- -- 3.5 -- -- 6 3.5 -- -- 3.5 -- -- -- -- -- -- -- -- -- -- -150 Min. Max. -- 6.7 2.6 2.6 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 150 -- -- -- 3.8 -- -- 6.7 3.5 -- -- 3.5 -- -- -- -- -- -- -- -- -- -- -133 Min. Max. -- 7.5 2.8 2.8 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 133 -- -- -- 4 -- -- 7.5 3.8 -- -- 3.8 -- -- -- -- -- -- -- -- -- -- -117 Min. Max. -- 8.5 3.4 3.4 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 117 -- -- -- 4 -- -- 8.5 4 -- -- 4 -- -- -- -- -- -- -- -- -- -- -5 Min. -- 10 4 4 -- 2.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max. 100 -- -- -- 5 -- -- 10 5 -- -- 5 -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid tKQLZ(1,2) Clock High to Output Low-Z tKQHZ(1,2) Clock High to Output High-Z tOEQ tOEQX (1) Output Enable to Output Valid Output Disable to Output Invalid tOELZ(1,2) Output Enable to Output Low-Z tOEHZ(1,2) Output Disable to Output High-Z tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 10 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH A16-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW4-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE2 CE2 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Single Write Burst Read Unselected Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 11 IC61SP12832 IC61SP12836 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 Symbol Parameter tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Min. 6 2.4 2.4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -150 Min. Max. 6.7 2.6 2.6 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -133 Min. Max. 7.5 2.8 2.8 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -117 Min. Max. 8.5 3.4 3.4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -5 Min. 10 4 4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A16-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW4-BW1 tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE DATAOUT High-Z tDS tDH DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 13 IC61SP12832 IC61SP12836 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 Symbol Parameter tKC tKH tKL tKQ tKQX (1) (1,2) Min. 6 2.4 2.4 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 0.5 0.5 0.5 2 2 Max. -- -- -- 3.5 -- -- 3.6 3.5 -- -- 3.5 -- -- -- -- -- -- -- -- -150 Min. Max. 6.7 2.6 2.6 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 0.5 0.5 0.5 2 2 -- -- -- 3.8 -- -- 6.7 3.5 -- -- 3.5 -- -- -- -- -- -- -- -- -133 Min. Max. 7.5 2.8 2.8 -- 1.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 0.5 0.5 0.5 2 2 -- -- -- 4 -- -- 7.5 3.9 -- -- 3.8 -- -- -- -- -- -- -- -- -117 Min. Max. 8.5 3.4 3.4 -- 2 0 1.5 -- 0 0 2 1.5 1.5 1.5 0.5 0.5 0.5 2 2 -- -- -- 4 -- -- 8.5 4 -- -- 4 -- -- -- -- -- -- -- -- -5 Min. 10 4 4 -- 2.5 0 1.5 -- 0 0 2 1.5 1.5 1.5 0.5 0.5 0.5 2 2 Max. -- -- -- 5 -- -- 10 5 -- -- 5 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Output Enable to Output Valid (1) tKQLZ tOEQ tKQHZ(1,2) Clock High to Output High-Z tOEQX tOELZ tAS tSS tCES tAH tSH tCEH tZZS tZZREC Output Disable to Output Invalid Output Enable to Output Low-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery (1,2) tOEHZ(1,2) Output Disable to Output High-Z Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 14 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 IC61SP12832 IC61SP12836 SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP ADSC ADV tAS tAH A16-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH CE tCES tCEH CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ tZZS tZZREC DATAIN ZZ High-Z Single Read Snooze with Data Retention Read Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 15 IC61SP12832 IC61SP12836 ORDERING INFORMATION Commercial Range: 0C to +70C Speed 166 MHz 150 MHz 133 MHz 117 MHz 100 MHz Order Part Number IC61SP12832-166TQ IC61SP12832-166B IC61SP12832-150TQ IC61SP12832-150B IC61SP12832-133TQ IC61SP12832-133B IC61SP12832-117TQ IC61SP12832-117B IC61SP12832-5TQ IC61SP12832-5B Package 14x20x1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA Speed 166 MHz 150 MHz 133 MHz 117 MHz 100 MHz Order Part Number IC61SP12836-166TQ IC61SP12836-166B IC61SP12836-150TQ IC61SP12836-150B IC61SP12836-133TQ IC61SP12836-133B IC61SP12836-117TQ IC61SP12836-117B IC61SP12836-5TQ IC61SP12836-5B Package 14x20x1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*22mm PBGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 16 Integrated Circuit Solution Inc. SSR019-0A 09/17/2001 |
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